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| www.irf.com 1 10/02/06 irlr7821pbfirlu7821pbf hexfet power mosfet notes through are on page 11 applications benefits very low rds(on) at 4.5v v gs ultra-low gate impedance fully characterized avalanche voltage and current high frequency synchronous buck converters for computer processor power high frequency isolated dc-dc converters with synchronous rectification for telecom and industrial use lead-free d-pak irlr7821pbf i-pak irlu7821pbf v dss r ds(on) max qg 30v 10m 10nc absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v i d @ t c = 100c continuous drain current, v gs @ 10v a i dm pulsed drain current p d @t c = 25c maximum power dissipation p d @t c = 100c maximum power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range thermal resistance parameter typ. max. units r jc junction-to-case CCC 2.0 r ja junction-to-ambient (pcb mount) CCC 50 c/w r ja junction-to-ambient CCC 110 w -55 to + 175 75 0.50 37.5 max. 65 47 260 20 30 downloaded from: http:///
2 www.irf.com s d g static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 30 CCC CCC v ? v dss / ? t j breakdown voltage temp. coefficient CCC 23 CCC mv/c r ds(on) static drain-to-source on-resistance CCC 7.5 10 m ? CCC 9.5 12.5 v gs(th) gate threshold voltage 1.0 CCC CCC v ? v gs(th) gate threshold voltage coefficient CCC -5.3 CCC mv/c i dss drain-to-source leakage current CCC CCC 1.0 a CCC CCC 150 i gss gate-to-source forward leakage CCC CCC 100 na gate-to-source reverse leakage CCC CCC -100 gfs forward transconductance 46 CCC CCC s q g total gate charge CCC 10 14 q gs1 pre-vth gate-to-source charge CCC 2.0 CCC q gs2 post-vth gate-to-source charge CCC 1.2 CCC nc q gd gate-to-drain charge CCC 2.5 CCC q godr gate charge overdrive CCC 4.3 CCC see fig. 16 q sw switch char g e (q gs2 + q gd ) CCC 3.7 CCC q oss output charge CCC 8.5 CCC nc t d(on) turn-on delay time CCC 11 CCC t r rise time CCC 4.2 CCC t d(off) turn-off delay time CCC 10 CCC ns t f fall time CCC 3.2 CCC c iss input capacitance CCC 1030 CCC c oss output capacitance CCC 360 CCC pf c rss reverse transfer capacitance CCC 120 CCC avalanche characteristics parameter units e as sin g le pulse avalanche ener gy mj i ar avalanche current a e ar repetitive avalanche ener gy mj diode characteristics parameter min. typ. max. units i s continuous source current CCC CCC 65 (body diode) a i sm pulsed source current CCC CCC 260 ( bod y diode ) v sd diode forward voltage CCC CCC 1.0 v t rr reverse recovery time CCC 26 38 ns q rr reverse recovery charge CCC 15 23 nc t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) mosfet symbol v gs = 4.5v, i d = 12a CCC v gs = 4.5v typ. CCC CCC i d = 12a v gs = 0v v ds = 15v t j = 25c, i f = 12a, v dd = 15v di/dt = 100a/s t j = 25c, i s = 12a, v gs = 0v showing the integral reverse p-n junction diode. v ds = v gs , i d = 250a v ds = 24v, v gs = 0v v ds = 24v, v gs = 0v, t j = 125c clamped inductive load v ds = 15v, i d = 12a conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 15a conditions 7.5 max. 230 12 ? = 1.0mhz v ds = 16v, v gs = 0v v dd = 15v, v gs = 4.5v i d = 12a v ds = 16v v gs = 20v v gs = -20v downloaded from: http:/// www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 1000 2.0 4.0 6.0 8.0 10.0 v = 15v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 175 c j t = 25 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 r , drain-to-source on resistance (normalized) ds(on) v = i = gs d 10v 65a 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.5v 20s pulse width tj = 25c vgs top 10v 4.5v 3.7v 3.5v 3.3v 3.0v 2.7v bottom 2.5v 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.5v 20s pulse width tj = 175c vgs top 10v 4.5v 3.7v 3.5v 3.3v 3.0v 2.7v bottom 2.5v t j , junction temperature (c) downloaded from: http:/// 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 10000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0.1 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 175 c j t = 25 c j 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec 024681 01 2 q g total gate charge (nc) 0 1 2 3 4 5 6 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 24v v ds = 16v i d = 12a downloaded from: http:/// www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70 t , case temperature ( c) i , drain current (a) c d limited by package 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 0.5 1.0 1.5 2.0 2.5 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a fig 10. threshold voltage vs. temperature downloaded from: http:/// 6 www.irf.com 25 50 75 100 125 150 175 0 200 400 600 800 1000 starting tj, junction temperature ( c) e , single pulse avalanche energy (mj) as i d top bottom 4.9a 8.5a 12a d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13. gate charge test circuit fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 12c. maximum avalanche energy vs. drain current r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 14a. switching time test circuit v ds 90%10% v gs t d(on) t r t d(off) t f fig 14b. switching time waveforms 1 0.1 % + - downloaded from: http:/// www.irf.com 7 fig 15. for n-channel hexfet power mosfets ? ? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - ? ! "# ? $%&% % ? " '' ? %&% %( & fig 16. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr downloaded from: http:/// 8 www.irf.com control fet !" # $ %& !" # #' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f ? ? ? ? ? ? + q g v g f () + q oss 2 v in f ? ? ? ? " ( %& !" %& !" " ) # * % + %& !" # # , # - . / # # synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f ( ) *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be-tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca-pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic downloaded from: http:/// www.irf.com 9 line a 34 rectifier logo irf r120 12 assembly lot code year 1 = 2001 dat e code part number week 16 116a int ernat ional as s emb led on ww 16, 2001 in the assembly line "a" or note: "p" in as s embly line pos ition example: lot code 1234 this is an irfr120 with assembly i ndicates "l ead- f r ee" product (optional) p = de s i gn at e s l e ad- f r e e a = assembly site code part number week 16 dat e code year 1 = 2001 rect ifier int ernat ional logo lot code assembly 34 12 irfr120 downloaded from: http:/// 10 www.irf.com 0 - . 78 line a logo international rect ifier or product (optional) p = de s i gnat e s l e ad- f r e e a = assembly site code irfu120 119a dat e code part number lot code assembly 56 78 year 1 = 2001 we e k 19 i ndi cates l ead-f r ee" as s e mb led on ww 19, 2001 in the assembly line "a" note: "p" in ass embly line position example: wit h as s e mb l y t his is an irfu120 lot code 5678 rect ifier international logo assembly lot code irfu120 56 part number we e k 19 dat e code year 1 = 2001 downloaded from: http:/// www.irf.com 11 repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 3.2mh r g = 25 ? , i as = 12a. pulse width 400s; duty cycle 2%. calculated continuous current based on maximum allowable junction temperature. package limitation current is 30a. when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 10/2006 0 - . tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch downloaded from: http:/// note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:/// |
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